najoNanosystems: Physics, Chemistry, MathematicsНаносистемы: физика, химия, математика2220-80542305-7971Университет ИТМО10.17586/2220-8054-2017-8-6-709-716najo-596Research ArticlePHYSICSФИЗИКА1-bit and 2-bit comparator designs and analysis for quantum-dot cellular automata1-bit and 2-bit comparator designs and analysis for quantum-dot cellular automataMallaiahA.MallaiahA.

Anthapuramu, A.P

Anthapuramu, A.P

malli797@gmail.comSwamyG. N.SwamyG. N.

Vijayawada, A.P

Vijayawada, A.P

PadmapriyaK.PadmapriyaK.

Kakinada, A.P

Kakinada, A.P

Research Scholar, JNTUAResearch Scholar, JNTUADepartment of EI&E, VR Siddhartha Engineering CollegeDepartment of EI&E, VR Siddhartha Engineering CollegeDepartment of ECE, JNTUKDepartment of ECE, JNTUK20171208202586709716Copyright © Mallaiah A., Swamy G.N., Padmapriya K., 20252025Mallaiah A., Swamy G.N., Padmapriya K.Mallaiah A., Swamy G.N., Padmapriya K.Данная работа распространяется под лицензией Creative Commons Attribution 4.0.This work is licensed under a Creative Commons Attribution 4.0 License.https://nanojournal.ifmo.ru/jour/article/view/596

In PCs, the number of arithmetic operations, the comparator is a vital equipment unit, consisting of complementary metal-oxide-semiconductor (CMOS) technology. Another procedure, referred to as Quantum Cellular Automata (QCA) will supplant the CMOS outlines, having leverage concerning zone, control utilization, and latency. The primary QCA circuits planned with the inverter and majority voter entryways. In this paper, we utilize the clocking method 180 out of phase clock crossover to outline the 1-bit comparator and compare with the current outcomes. The new proposed wire crossing plan lessens the quantity of cells required to configuration, power and area necessities. Additionally, we planned 2-bit comparator having 11 majority gates (voters), 2 number of crossovers with 0.38 µm2 area, 203 number of cells. The designed 1-bit comparator contrast and the past outcomes where cells, region, delay demonstrates 53.57 %, 50 % and 33.32 % improvement respectively.

In PCs, the number of arithmetic operations, the comparator is a vital equipment unit, consisting of complementary metal-oxide-semiconductor (CMOS) technology. Another procedure, referred to as Quantum Cellular Automata (QCA) will supplant the CMOS outlines, having leverage concerning zone, control utilization, and latency. The primary QCA circuits planned with the inverter and majority voter entryways. In this paper, we utilize the clocking method 180 out of phase clock crossover to outline the 1-bit comparator and compare with the current outcomes. The new proposed wire crossing plan lessens the quantity of cells required to configuration, power and area necessities. Additionally, we planned 2-bit comparator having 11 majority gates (voters), 2 number of crossovers with 0.38 µm2 area, 203 number of cells. The designed 1-bit comparator contrast and the past outcomes where cells, region, delay demonstrates 53.57 %, 50 % and 33.32 % improvement respectively.

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The authors declare that there are no conflicts of interest present.