1-bit and 2-bit comparator designs and analysis for quantum-dot cellular automata
https://doi.org/10.17586/2220-8054-2017-8-6-709-716
Abstract
In PCs, the number of arithmetic operations, the comparator is a vital equipment unit, consisting of complementary metal-oxide-semiconductor (CMOS) technology. Another procedure, referred to as Quantum Cellular Automata (QCA) will supplant the CMOS outlines, having leverage concerning zone, control utilization, and latency. The primary QCA circuits planned with the inverter and majority voter entryways. In this paper, we utilize the clocking method 180 out of phase clock crossover to outline the 1-bit comparator and compare with the current outcomes. The new proposed wire crossing plan lessens the quantity of cells required to configuration, power and area necessities. Additionally, we planned 2-bit comparator having 11 majority gates (voters), 2 number of crossovers with 0.38 µm2 area, 203 number of cells. The designed 1-bit comparator contrast and the past outcomes where cells, region, delay demonstrates 53.57 %, 50 % and 33.32 % improvement respectively.
About the Authors
A. Mallaiah
Research Scholar, JNTUA
India
India
Anthapuramu, A.P
G. N. Swamy
Department of EI&E, VR Siddhartha Engineering College
India
India
Vijayawada, A.P
K. Padmapriya
Department of ECE, JNTUK
India
India
Kakinada, A.P
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Review
For citations:
Mallaiah A., Swamy G.N., Padmapriya K. 1-bit and 2-bit comparator designs and analysis for quantum-dot cellular automata. Nanosystems: Physics, Chemistry, Mathematics. 2017;8(6):709-716. https://doi.org/10.17586/2220-8054-2017-8-6-709-716
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