1-bit and 2-bit comparator designs and analysis for quantum-dot cellular automata

A. Mallaiah – Research Scholar, JNTUA, Anthapuramu, A.P, India; malli797@gmail.com
G. N. Swamy – Department of EI&E, VR Siddhartha Engineering College, Vijayawada, A.P, India
K. Padmapriya – Department of ECE, JNTUK, Kakinada, A.P, India

In PCs, the number of arithmetic operations, the comparator is a vital equipment unit, consisting of complementary metal-oxide-semiconductor (CMOS) technology. Another procedure, referred to as Quantum Cellular Automata (QCA) will supplant the CMOS outlines, having leverage concerning zone, control utilization, and latency. The primary QCA circuits planned with the inverter and majority voter entryways. In this paper, we utilize the clocking method 180 out of phase clock crossover to outline the 1-bit comparator and compare with the current outcomes. The new proposed wire crossing plan lessens the quantity of cells required to configuration, power and area necessities. Additionally, we planned 2-bit comparator having 11 majority gates (voters), 2 number of crossovers with 0.38 μm2 area, 203 number of cells. The designed 1-bit comparator contrast and the past outcomes where cells, region, delay demonstrates 53.57 %, 50 % and 33.32 % improvement respectively.

Keywords: QCA design, wire crossing, comparator, Ex OR gate.

PACS 03.65.Xp , 03.67.Hk , 03.67.Lx, 05.60.Gg

DOI 10.17586/2220-8054-2017-8-6-709-716


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