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NANOSYSTEMS: PHYSICS, CHEMISTRY, MATHEMATICS, 2017, 8 (1), P. 75–78

Simulation of DIBL effect in junctionless SOI MOSFETs with extended gate

A. E. Atamuratov – Urganch State University, Kh. Olimjan, 14, Urganch, 220100, Uzbekistan; atabek.atamuratov@yahoo.com
M. Khalilloev – Urganch State University, Kh. Olimjan, 14, Urganch, 220100, Uzbekistan
A. Abdikarimov – Urganch State University, Kh. Olimjan, 14, Urganch, 220100, Uzbekistan
Z. A. Atamuratova – Urganch State University, Kh. Olimjan, 14, Urganch, 220100, Uzbekistan
M. Kittler – Technical University of Ilmenau, Ehrenbergstrasse, 29, 98693 Ilmenau, Germany
R. Granzner – Technical University of Ilmenau, Ehrenbergstrasse, 29, 98693 Ilmenau, Germany
F. Schwierz – Technical University of Ilmenau, Ehrenbergstrasse, 29, 98693 Ilmenau, Germany; frank.schwierz@tuilmenau.de

Short channel effects such as DIBL are compared for trigate SOI Junctionless MOSFET with extended and non-extended lateral part of the gate. A trigate SOI JLMOSFET with gate length Lgate, a silicon body width Wtin and thickness of 10 nm are simulated. In order to calculate the DIBL, the transfer characteristics of JLMOSFETs was simulated at a donor concentration of 5*1019 cm-3 in the silicon body. The equivalent oxide thicknesses of the HfO2 gate insulator used in simulation was 0.55 nm. Simulation result showed the DIBL for the trigate JLMOSFET depended on the length of the lateral part of the gate Lext. DIBL is high for devices with gates having extended lateral parts. This is a result of parasitic source (drain)-gate capacitance coupling which is higher for longer Lext.

Keywords: Junctionless MOSFET, DIBL, parasitic capacitance.

PACS 85.30.Tv

DOI 10.17586/2220-8054-2017-8-1-75-78

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